第7章 VHDL语句(2)

...PROCESS BEGIN

...WAIT ON s1,s2 ; END PROCESS ;

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7.1 顺序语句7.1.7 WAIT语句

【例7-10】 (a) WAIT_UNTIL结构 ... Wait until enable ='1'; ... (b) WAIT_ON结构 LOOP Wait on enable; EXIT WHEN enable ='1'; END LOOP;

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7.1 顺序语句7.1.7 WAIT语句WAIT UNTIL 信号=Value ; WAIT UNTIL 信号’EVENT AND 信号=Value; WAIT UNTIL NOT 信号’STABLE AND 信号=Value; -- (1) -- (2) -- (3)

WAIT UNTIL clock ='1';

WAIT UNTIL rising_edge(clock) ;WAIT UNTIL NOT clock’STABLE AND clock ='1'; WAIT UNTIL clock ='1' AND clock’EVENT;

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7.1 顺序语句7.1.7 WAIT语句【例7-11】 PROCESS BEGIN WAIT UNTIL clk ='1'

; ave <= a; WAIT UNTIL clk ='1'; ave <= ave + a; WAIT UNTIL clk ='1'; ave <= ave + a; WAIT UNTIL clk ='1'; ave <= (ave + a)/4 ; END PROCESS ;

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7.1 顺序语句7.1.7 WAIT语句【例7-12】 PROCESS BEGIN

rst_loop : LOOPWAIT UNTIL clock ='1' AND clock’EVENT; -- 等待时钟信号 NEXT rst_loop WHEN (rst='1'); -- 检测复位信号rst

x <= a ;

-- 无复位信号，执行赋值操作

WAIT UNTIL clock ='1' AND clock’EVENT; -- 等待时钟信号 NEXT rst_loop When (rst='1'); y <= b ; END LOOP rs -- 检测复位信号rst -- 无复位信号，执行赋值操作

【例7-13】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shifter IS PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); shift_left: IN STD_LOGIC; shift_right: IN STD_LOGIC; clk: IN STD_LOGIC; reset : IN STD_LOGIC; mode : IN STD_LOGIC_VECTOR (1 DOWNTO 0); qout : BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0) ); END shifter; ARCHITECTURE behave OF shifter IS SIGNAL enable: STD_LOGIC; BEGIN PROCESS BEGIN WAIT UNTIL (RISING_EDGE(clk) ); --等待时钟上升沿 IF (reset = '1') THEN qout <= "00000000"; ELSE CASE mode IS WHEN "01" => qout<=shift_right & qout(7 DOWNTO 1); WHEN "10" => qout<=qout(6 DOWNTO 0) & shift_left; WHEN "11" => qout <= data; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; END behave;

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--右移 --左移 -- 并行加载

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7.1 顺序语句7.1.8 RETURN语句

返回语句RETURN有两种语句格式：

RETURN; RETURN 表达式；

-- 第一种语句格式 -- 第二种语句格式

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