ug_sopc_builder-Altera FPGA嵌入式软核开发官方教程(5)

information about your SOPC Builder system. The .qip file includes references to

the following information:

■

HDL files used in the SOPC Builder system ■

TimeQuest Timing Analyzer Synopsys Design Constraint (.sdc ) files ■Component definition files for archiving purposes

After you generate the SOPC Builder system, you can compile it with the Quartus II

software, or you can instantiate it in a larger FPGA design.

Creating a Memory Map for Software Development

When your SOPC Builder system includes a Nios II processor, SOPC Builder

generates a header file, cpu.h , that provides the base address of each Avalon-MM

slave component. In addition, each slave component can provide software drivers

and other software functions and libraries for the processor. You can create C header

files for your system using the sopc-create-header-files utility.

f For details type sopc-create-header-files --help in a Nios II Command shell.

f For more details about how to provide Nios II software drivers for components, refer

to the Developing Device Drivers for the Hardware Abstraction Layer chapter of the Nios II

Software Developer’s Handbook . The Nios II EDS is separate from SOPC Builder, but it

uses the output of SOPC Builder as the foundation for software development.

Creating a Simulation Model and Test Bench

You can simulate your system after generating it with SOPC Builder. During system

generation, SOPC Builder outputs a simulation test bench and a ModelSim setup

script that eases the system simulation effort. The test bench does the following:

■

Instantiates the SOPC Builder system ■

Drives all clocks and resets ■Instantiates simulation models for off-chip devices when available

SOPC Builder Design Flow

Figure 1–2 illustrates an example bottom-up design flow in SOPC Builder which

starts with component design. As this flow diagram illustrates, the typical design flow

includes the following high-level steps:

1.Package your component for SOPC Builder using the Component Editor.

Chapter 1:Introduction to SOPC Builder1–7 SOPC Builder Design Flow

2.Simulate at the unit-level, possibly incorporating Avalon BFMs to verify the

system.

b9e4216eaeaad1f346933fb2plete the SOPC Builder design by adding other components, specifying

interrupts, clocks, resets, and addresses.

4.Generate the SOPC Builder system.

5.Perform system level simulation.

6.Constrain and compile the design.

7.Download the design to an Altera device.

8.Test in hardware.

Figure1–b9e4216eaeaad1f346933fb2plete Qsys Design Flow

December 2010Altera Corporation SOPC Builder User Guide

1–8Chapter 1:Introduction to SOPC Builder

Visualization of SOPC Builder Systems 1In the alternative top-down valid design flow, you begin by designing the SOPC Builder system and then define and instantiate custom SOPC Buildder component.

This approach clarifies the system requirements earlier in the design process.

Designs targeting HardCopy devices are require specific design constraints.

Consequently, if you are targeting a HardCopy series device, you must verify you

design for the HardCopy companion device.

Follow these guidelines to verify your design for both devices:

1.In the Quartus II Device dialog box, select both the FPGA and the appropriate

HardCopy companion device.

2.In Step 8 of the design flow shown in Figure1–2, compile for both the FPGA and

HardCopy device.

3.After Step 10 of the design flow shown in Figure1–2, if FPGA passes all functional

simulation and hardware verification tests, generate the HardCopy handoff

archive and send this archive to the HardCopy Design Center for the backend flow

and tapeout.

Visualization of SOPC Builder Systems

You can use the Filters dialog box to customize the display of your system in the

connections panel. You can filter the display of your system by interface type, instance

name, interface type, or using custom tags. For example, you can use filtering to view

only instances that include an Avalon-MM interface or instances that are connected to

a particular Nios II processor. For more information, refer to Quartus II online Help.

Operating System Support

SOPC Builder supports all of the operating systems that the Quartus II software

supports.

f For details on installation and licensing, refer to the Altera Software Installation and

Licensing Manual.

Talkback Support

Talkback is a Quartus II software feature that provides feedback to Altera on tool and

IP feature usage. Altera uses the data to help guide future product planning efforts.

Talkback sends Altera information on the Altera components you use, including:

interface types, interface properties, parameter names and values, clocking, and

software assignments. For components from Altera, Talkback sends the component

parameter values to help understand what features of the component are being used.

For non-Altera components, Talkback collects information about how interfaces such

as Avalon-MM are being used. Connectivity between components is not sent. The

Talkback file does not include information about system connectivity, interrupts, or

the memory map seen by each master in the system. Talkback collects the same very

general information about your proprietary components.

The Talkback feature is enabled by default. You can disable Talkback from within the

Quartus II software if you do not wish to share your usage data with Altera.

SOPC Builder User Guide December 2010Altera Corporation

2.System Interconnect Fabric for

Memory-Mapped Interfaces The system interconnect fabric for memory-mapped interfaces is a high-bandwidth

interconnect structure for connecting components that use the Avalon?

Memory-Mapped (Avalon-MM) interface. The system interconnect fabric consumes

less logic, provides greater flexibility, and higher throughput than a typical shared

system bus. It is a cross-connect fabric and not a tristated or time domain multiplexed

bus. This chapter describes the functions of system interconnect fabric for

memory-mapped interfaces and the implementation of those functions.

High-Level Description

The system interconnect fabric is the collection of interconnect and logic resources

that connects Avalon-MM master and slaves on components in a system. SOPC

Builder generates the system interconnect fabric to match the needs of the

components in a system. The system interconnect fabric implements the connection

details of a system. It guarantees that signals are routed correctly between master and

slaves, as long as the ports adhere to the rules of the Avalon Interface Specifications. This

chapter provides information on the following topics:

■“Address Decoding” on page2–3

■“Datapath Multiplexing” on page2–4

■“Wait State Insertion” on page2–5

■“Pipelined Read Transfers” on page2–6

■“Dynamic Bus Sizing and Native Address Alignment” on page2–6

■“Arbitration for Multimaster Systems” on page2–9

■“Burst Adapters” on page2–14

■“Interrupts” on page2–15

■“Reset Distribution” on page2–16

f For details about the Avalon-MM interface, refer to the Avalon Interface Specifications.

System interconnect fabric for memory-mapped interfaces supports the following

items:

■Any number of master and slave components. The master-to-slave relationship can be one-to-one, one-to-many, many-to-one, or many-to-many.

■On-chip components.

■Interfaces to off-chip devices.

■Master and slaves of different data widths.

■Components operating in different clock domains.

■Components using multiple Avalon-MM ports.

December 2010Altera Corporation SOPC Builder User Guide

2–2

Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces

High-Level Description

SOPC Builder User Guide December 2010Altera Corporation

Figure 2–1 shows a simplified diagram of the system interconnect fabric in an example memory-mapped system with multiple masters.

1

All figures in this chapter are simplified to show only the particular function being discussed. In a complete system, the system interconnect fabric might alter the

address, data, and control paths beyond what is shown in any one particular figure.

SOPC Builder supports components with multiple Avalon-MM interfaces, such as the processor component shown in Figure 2–1. Because SOPC Builder can create system interconnect fabric to connect components with multiple interfaces, you can create complex interfaces that provide more functionality than a single Avalon-MM

interface. For example, you can create a component with two different Avalon-MM slaves, each with an associated interrupt interface.

System interconnect fabric can connect any combination of components, as long as each interface conforms to the Avalon Interface Specifications . It can, for example, connect a system comprised of only two components with unidirectional dataflow between them. Avalon-MM interfaces are suitable for random address transactions, such as to memories or embedded peripherals.

Figure 2–1.System Interconnect Fabric—Example System

Write Data & Control Si g nals Read Data

Interface to Off-Chip Device

M S

Avalon-MM Master Port

Avalon-MM Slave Port

Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces2–3 Fundamentals of Implementation

Generating system interconnect fabric is SOPC Builder’s primary purpose. In most

cases, you are not required to modify the generated HDL; however, a basic

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