ug_sopc_builder-Altera FPGA嵌入式软核开发官方教程(6)

understanding of how HDL works can help you optimize your system. For example,

knowledge of the arbitration algorithm can help designers of multimaster systems

minimize the impact of arbitration on the system throughput.

Fundamentals of Implementation

System interconnect fabric for memory-mapped interfaces implements a partial

crossbar interconnect structure that provides concurrent paths between master and

slaves. System interconnect fabric consists of synchronous logic and routing resources

inside the FPGA.

For each component interface, system interconnect fabric manages Avalon-MM

transfers, interacting with signals on the connected component. Master and slave

interfaces can contain different signals and the system interconnect fabric handle any

adaptation necessary between them. In the path between master and slaves, the

system interconnect fabric might introduce registers for timing synchronization, finite

state machines for event sequencing, or nothing at all, depending on the services

required by the specific interfaces.

f For more information, refer to the Avalon Memory-Mapped Design Optimizations

chapter in the Embedded Design Handbook.

Functions of System Interconnect Fabric

System interconnect fabric logic provides the following functions:

■“Address Decoding” on page2–3

■“Datapath Multiplexing” on page2–4

■“Wait State Insertion” on page2–5

■“Pipelined Read Transfers” on page2–6

■“Arbitration for Multimaster Systems” on page2–9

■“Burst Adapters” on page2–14

■“Interrupts” on page2–15

■“Reset Distribution” on page2–16

The behavior of these functions in a specific SOPC Builder system depends on the

design of the components in the system and the settings made in SOPC Builder. The

remaining sections of this chapter describe how SOPC Builder implements each

function.

Address Decoding

Address decoding logic in the system interconnect fabric forwards appropriate

addresses to each slave. Address decoding logic simplifies component design in the

following ways:

December 2010Altera Corporation SOPC Builder User Guide

2–4Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces

Datapath Multiplexing

SOPC Builder User Guide December 2010Altera Corporation ■The system interconnect fabric selects a slave whenever it is being addressed by a

master. Slave components do not need to decode the address to determine when

they are selected.

■Slave addresses are properly aligned to the slave interface.

■

Changing the system memory map does not involve manually editing HDL. Figure 2–2 shows a block diagram of the address-decoding logic for one master and

two slaves. Separate address-decoding logic is generated for every master in a system.

As Figure 2–2 shows, the address decoding logic handles the difference between the

master address width () and the inpidual slave address widths ( and ).