bucuo de dongxi
(Paste from your simulation waveforms)
VIII. Functional Verification
The test bench contains an instance of module i2s_top and a clone (i2s_master) of ADC that outputs bit clock, word clock, and data bit. Parameters can be set in the i2s_master to output various audio sampling frequencies, bits per word, and signal types for maximum verification coverage. A mechanism that automatically checks the audio PCM values when those samples are outputted to DDR2 data bus is built in. Necessary data files for verification are generated beforehand using a C-program. The testbench then reads the data files, creats input signals to i2s_top, and checks against the outputs from i2s_top at the appropriate cycle timings.
Test cases from all possible combinations of 12, 16, 20, 24, 32 bits/sample, 32, 44.1, 48, 96, 192 kHz sampling rate are created, resulting in a total of 50 cases. In each test case, the number of samples is equal to 2**min{bits/sample, 24} for each left and right channels. The values in the adjacent samples are incremented or decremented in a systematic way. The simulation results show that the design can deal with all these test cases correctly; there is no mismatch at the check points.
In the test bench, the register values which suppose to be set by CPU are forced to desired ones. The true interface functions with CPU are not verified until it is integrated with CPU and firmware. Nevertheless, a simple separate test shows that the read and write mechanism functions correctly when register address values over the register address bus belong to the module.
………………
IX. Performance Related
From the simulation, the cycle count (based on the clk) per capture of 8 samples is xxx.
The design is synthesized with clk=250 MHz, bitclk=500 kHz, clk uncertainty=0.2 ns, bitclk uncertainty=5ns, using the UMC 90 nm library XXXXX and ARM memory compiler YYYY. The resulting combinational and non-combinational areas are xxxx and yyyy, respectively. The memory area for the two register files in the design is zzzz. …….
Appendix A: Asynchronous design
There are two clocks in the design; one is bitclk and the other clk. A control signal xxxx is created based on bitclk in the i2s_capture module. The control signal is then synchronized with 3 stages of flip-flops in clk domain. A one clk cycle long strobe yyyy is then created and used for all functions in clk domain as shown in Figure A.1.
搜索“diyifanwen.net”或“第一范文网”即可找到本站免费阅读全部范文。收藏本站方便下次阅读,第一范文网,提供最新人文社科Design_Spec_template(7)全文阅读和word下载服务。
相关推荐: