Intellectual property metering(14)

4.2 Disconnection Approach

In this approach, an additional finite state machine (FSM) is designed to facilitate design identification. Checking the ID of the design, requires an unused state of the other FSMs that are part of the design. Modern designs have a large number of FSM with numerous unused states/input combinations (don’t cares). The added FSM, is the same for all the designs in the mask level. In the postprocessing step, lasers burn some of the connections of this added FSM in each design and thus generates different states and functions of it. This added FSM is different in each design since we laser burn different connections in each design to achieve a slightly different control path. The algorithms to decide exactly where to burn the interconnect in each chip, can be derived from a computer simulation of the state machine to derive unique ID for each of them. This solution does not need any extra processing steps and is much faster and more robust than the previous approaches. Another alternative, is to use BISR mechanism for hardware metering. BISR designs are designs which have built in self repair fault tolerance that can function properly even if some parts of the design are faulty [17]. The idea here is to intentionally induce variety of faults in BISR designs in such a way that each design has different faulty parts. Note that while repairing circuits using BISR is relatively expensive, inducing faults is relatively cheap.

4.3 Fingerprinting by using the SiidTech Approach

This solution uses the same methodology as the disconnection approach mentioned in the last section. The difference is that the added FSM is now reading out the unique finger-print proposed by the SiidTech Corporation [23].

SiidTech approach, which identifies each chip by detecting imbalances in threshold voltages-discrepancies unavoidably formed during fabrication. The advantage of this approach is also that no external programming or special processing steps are needed. A silicon fingerprint is generated at “birth” - during the fabrication of the die - and is carried throughout the silicon’s useful life. The disadvantages of this approach are the same as for the generic Siid technology that was elaborated in Section 2.

4.4 Software Metering

The proposed hardware metering techniques are directly applicable to software metering. Actually, it is significantly easier to create software tracking techniques, since there is no technological constraints associated with integrated circuit manufacturing process. One alternative is to just add static variants in software executables, by imposing constraints during compilation. The constraint can be either local or global.

Another alternative for hardware and software metering is to use dynamic data struc-tures as ID carriers. This approach has been already used for software protection through watermarking [8]. The authors propose a combination of code obfuscation with creation of multiple versions for a set of dynamic data structures created during the program execu-tion.

The idea of dynamic creation of ID can be applied for software metering. We propose radically different approach to this task. We add an extra software module which is the ID carrier. For each copy this module is differently configured. The module is invoked from

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