Intellectual property metering(8)

Abstract. We have developed the first hardware and software (intellectual property) metering scheme that enables reliable low overhead proofs for the number of manufactured parts and copied programs. The key idea is to make each design slightly different d

Inc., an Oregon start-up company, has proposed an approach for integrated circuit identifi-cation from random threshold mismatches in an array of addressable MOSFETs. The tech-nique leverages on process discrepancies unavoidably formed during fabrication. This analog technique can be used in tracking semiconductor dies, authentication and intellec-tual property (IP) tagging. In a recent report of this method’s measured performance[23], for a 0.35um poly CMOS, for generating 112 ID bits, 132 blocks area used, each with the area of 252x93um. The IDs proposed by SiidTech are not deterministic and these IDs can not be deterministically compacted. Also, due to the birthday paradox, there is still a small probability that two IDs generated randomly have the same value. Component applica-tions enables the user to trace a particular die on a wafer and store this information for future usages. There are several advantages of our scheme over the Siid scheme. We have been able to obtain more than 1.3E12 distinct solutions even in our smallest test cases which have only 15 registers (Our number of solutions will go exponentially high by using a few more registers). Furthermore, our IDs are deterministic and therefore they can be used to contain a defined signature to be used in many cryptographic schemes.

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