end else if(key2_low) begin
fen=fen-1'b1; if(fen==0) begin shi=shi-1'b1; fen=59; end end else begin shi<=shi; fen<=fen; miao<=miao; end
end endmodule
//显示部分
module xianshi(clk,rst_n,en_1ms,shi,fen,miao,led_bit,dataout); input clk; input rst_n; input en_1ms; input[5:0] shi; input[5:0] fen; input[5:0] miao;
output[7:0] led_bit; //位选 output[7:0] dataout; //段选
//数码管显示 0~9 对应段选输出
parameter num0 = 8'b11000000, num1 = 8'b11111001, num2 = 8'b10100100, num3 = 8'b10110000, num4 = 8'b10011001, num5 = 8'b10010010, num6 = 8'b10000010, num7 = 8'b11111000, num8 = 8'b10000000, num9 = 8'b10010000;
reg[3:0] shi1,shi2,fen1,fen2,miao1,miao2; reg[7:0] led_bit; //位选 reg[7:0] dataout; //段选
reg[2:0] state; //状态寄存器
always@(posedge clk or negedge rst_n) if(!rst_n) begin led_bit<=8'b1; state<=3'b0; end
else if(en_1ms) begin state<=state+1'b1;
shi1=shi/10; shi2=shi; fen1=fen/10; fen2=fen; miao1=miao/10; miao2=miao; if(state==3'b000) begin led_bit=8'b11111110; case(miao2) 0: dataout<=num0; 1: dataout<=num1; 2: dataout<=num2; 3: dataout<=num3; 4: dataout<=num4; 5: dataout<=num5; 6: dataout<=num6; 7: dataout<=num7; 8: dataout<=num8; 9: dataout<=num9; default :dataout<=num0; endcase end
else if(state==3'b001) begin led_bit=8'b11111101; case(miao1)
0: dataout<=num0; 1: dataout<=num1; 2: dataout<=num2; 3: dataout<=num3; 4: dataout<=num4; 5: dataout<=num5; default :dataout<=num0; endcase end else if(state==3'b010) begin led_bit=8'b11110111; case(fen2) 0: dataout<=num0; 1: dataout<=num1; 2: dataout<=num2; 3: dataout<=num3; 4: dataout<=num4; 5: dataout<=num5; 6: dataout<=num6; 7: dataout<=num7; 8: dataout<=num8; 9: dataout<=num9; default :dataout<=num0; endcase end else if(state==3'b011) begin led_bit=8'b11101111; case(fen1) 0: dataout<=num0; 1: dataout<=num1; 2: dataout<=num2; 3: dataout<=num3; 4: dataout<=num4; 5: dataout<=num5; endcase end else if(state==3'b100) begin
led_bit=8'b10111111; case(shi2) 0: dataout<=num0; 1: dataout<=num1; 2: dataout<=num2; 3: dataout<=num3; 4: dataout<=num4; default :dataout<=num0; endcase end else if(state==3'b101) begin led_bit=8'b01111111; case(shi1) 0: dataout<=num0; 1: dataout<=num1; 2: dataout<=num2; endcase end else if(state==3'b110) begin led_bit=8'b11011011; dataout<=8'b10111111; end end else
begin
dataout<=dataout; led_bit<=led_bit; end endmodule
//顶层模块
module Shizhong(clk,rst_n,key1,key2,led_bit,dataout); input clk; input rst_n; input key1; input key2;
output[7:0] led_bit; output[7:0] dataout;
wire en_1s; wire en_1ms; wire[5:0] shi;
wire[5:0] fen; wire[5:0] miao;
wire key1_low,key2_low; fenpin fenpin_int(.clk(clk),
.rst_n(rst_n), .en_1s(en_1s), .en_1ms(en_1ms) ); anjian anjian_int(.clk(clk),
.rst_n(rst_n), .key1(key1), .key2(key2), .key1_low(key1_low), .key2_low(key2_low) ); shijian shijian_int(.clk(clk),
.rst_n(rst_n), .en_1s(en_1s), .key1_low(key1_low), .key2_low(key2_low), .shi(shi), .fen(fen), .miao(miao) );
xianshi xianshi_int(.clk(clk),
.rst_n(rst_n), .en_1ms(en_1ms), .shi(shi), .fen(fen), .miao(miao), .led_bit(led_bit), .dataout(dataout) );
endmodule
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