5962R9689104VYC中文资料(5)

READ CYCLE

A combination of PE greater than VIH(min), and CE less than VIL(max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output.

An address access read is initiated by a change in address inputs while the chip is enabled with OE asserted and PE deasserted. Valid data appears on data output, DQ(7:0), after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time.

AC CHARACTERISTICS READ CYCLE (Post-Radiation)*(VDD = 5.0V ±10%; -55°C < TC < +125°C)

SYMBOLtAVAV1tAVQVtAXQX2tGLQX2tGLQVtGHQZtELQX2 tELQV tEHQZ

PARAMETERRead cycle timeRead access timeOutput hold time

OE-controlled output enable time OE-controlled access timeOE-controlled output three-state timeCE-controlled output enable timeCE-controlled access time CE-controlled output three-state time

The chip enable-controlled access is initiated by CE going active while OE remains asserted, PE remains deasserted, and the addresses remain stable for the entire cycle. After the specified tELQV is satisfied, the eight-bit word addressed by A(14:0) appears at the data outputs DQ(7:0).

Output enable-controlled access is initiated by OE going active while CE is asserted, PE is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tELQV have not been satisfied.

28F256-45 MIN MAX45

45

00

1515

4515

28F256-40 MIN MAX40

40

00

1515

4015

UNITnsnsnsnsnsnsnsnsns

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads(Si).1. Functional test.

2. Three-state is defined as a 400mV change from steady-state output voltage.

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