C
CLK0_T CLK0_C
[41][41] CA[0..9][41]
B
B
IC-MT6735-LP2-E1-SBS_MAP0827
A
A
Title Size B Date:5 4 3 2
13_BB_3
MTK ConfidentialWednesday, January 14, 2015 Sheet1
13
of
99
5
4
3
2
1
U2001A
[65,90] PWRKEY[65][11,90] HOMEKEY SYSRSTB HOMEKEY
E2 N6 D3 D2
CONTROL SIGNALPWRKEY HOMEKEY RESETB EXT_PMIC_EN
BUCK OUTPUTVPROC VPROC VPROC VPROC VPROC
L2001 PL/ 0.33/ uH/ 2520
A7 B7 C7 D7 B8
VPROC_SW
1
2
125mil VPROC_PMU
[11]
WATCHDOG D_GND
M7 1 2 R2003R/ 200/ K/ 0201 R0201
VPROC_FB AVSS45_VPROC_FB WDTRSTB_IN UVLO_VTH FSOURCE PMU_TESTMODE SRCLKEN_IN0 SRCLKEN_IN1 SPI_CSN SPI_CLK SPI_MOSI SPI_MISO VCORE1 VCORE1 VCORE1 VCORE1_FB AVSS45_VCORE1_FB VLTE_FB AVSS45_VLTE_FB VLTE VLTE VLTE
C16 B15
4 mil GND trace with good shielding from baseband (Differential) VPROC_PMIC_FB_6328 VPROC_PMIC_FB_6328[10] GND_VPROC_PMIC_FB_6328 GND_VPROC_PMIC_FB_6328[10] L2003 PL/ 0.47/ uH/ 2016
N2 P4 D4 P8 R5 M6 K6
D
UVLO_VTH R RANGE: 200KOHM~ 250KOHM[11][11] SRCLKENA0 SRCLKENA1
D_GND
A12 B12 C12
VLTE_SW
1
2
75mil VLTE_PMUD
4 mil GND trace with good shielding (Differential)
C14 E13
VLTE_PMIC_FB GND_VLTE_FB
VLTE_PMIC_FB GND_VLTE_FB
[10][10]
[11] PWRAP_SPI0_CSN[11] PWRAP_SPI0_CK[11] PWRAP_SPI0_MO[11] PWRAP_SPI0_MI PWRAP_SPI0_MO PWRAP_SPI0_MI
L2006 PL/ 0.47/ uH/ 2016
L6 N5 R15
A5 A6 B5 C2 C1
VCORE_SW
1
2
90mil
VCORE_PMU
AUX ADCVAUX18
VCORE_PMIC_FB VCORE_PMIC_FB GND_VCORE_FB GND_VCORE_FB 4 mil GND trace with good shielding from baseband (Differential)
[10][10]
1VBAT C2023
2C/ 1/ uF/ 0201 C0201
M12 N13 P14
AVDD18_AUXADC AVSS18_AUXADC AUXADC_VINL2008
Please refer to latest MMD designNC/MMD/PMIC 100mil SH2009
D_GND
1
2
BAT_VPROC
VBAT INPUT50mil
VSYS22 VSYS22 VSYS22_FB
B10 B11 C10 D10C2007 C/ 22/ uF/ 0603 C0603 NC/MMD/PMIC SH2010
AVDD45_VPROC AVDD45_VPROC AVDD45_VPROC AVDD45_VPROC AVDD45_VLTE AVDD45_VLTE AVDD45_VLTE AVDD45_VCORE1 AVDD45_VCORE1 AVDD45_VCORE1 AVDD45_VSYS22 AVDD45_VSYS22 AVDD45_VPA AVDD45_SMPS
C3
1
L2009
2
1NC/MMD/PMIC
2SH2011
BAT_VLTE
30mil 30mil
1D_GND
2
BAT_VCORE1
B13 C13 D13 C4 C5 B4 A1 B1 A16 C15
VPA VPA_FB
A15 B14
VPA_SW
1 1
2 PL/ 2.2/ uH/ 2520 1
30mil C2055 C/ 2.2/ uF/ 0402 C0402
D_GND VPA_PMU
NC/MMD/PMIC
SH2012
2
C2049 C0201 C/ 1/ nF/ 0201/ 16V/ NC
11. VBAT_Buck input cap should connect to its individual GND first, then go to main GND. 2. Buck controller power trace (AVDD
45_SMPS) must use single trace connected to system (battery) power directly, and can’t merge with others. 3. Please refer to latest MMD design NC/MMD/PMIC 1 NC/MMD/PMIC 1
2 2 SH2013 2 SH2014
BAT_VSYS BAT_VPA
30mil 30mil 4mil
LDO OUTPUTVM VTCXO_0 VTCXO_1 VRF18_0 VRF18_1 VSIM1 VSIM2 VCN18 VCN28 VCN33 VIO18 VUSB33 VIO28 TREF VEFUSE VMC VMCH VEMC_3V3 VCAMA VCAMAF VCAMD VCAMIO VGP1 VSRAM
J1 P9 T16 F10 F9 R11 N11 F3 R13 R12 F2 P11 K2 P13 T15 K4 R9 R10 T14 H5 H2 E3 H4 E4
D_GND
D_GND VM VTCXO_0_PMU VRF18_0_PMU VSIM1_PMU VSIM2_PMU
2R2005 R/ 1/ ohm/ 0201 R0201
1 1
2
D_GND 20mil 20mil 20mil 20mil 20mil
2
2
4 mil GND trace with good shielding from baseband (Differential)
1
A2 B2
VSYS_SW
50mil
1
2
PL/ 0.47/ uH/ 2016
50mil
VSYS_PMU C2039 C/ 10/ uF/ 0603 C0603
C2043 C/ 1/ uF/ 0201 C0201
VBATC
120mil
T13 T8 K1 T11 M2
AVDD45_LDO1 AVDD45_LDO2 AVDD45_LDO3 AVDD45_LDO4 AVDD45_LDO5
VCN18_PMU VCN28_PMU VCN33_PMU VIO18_PMU VUSB33_PMU VIO28_PMU VBATREF VEFUSE VMC_PMU VMCH_PMU VEMC_3V3_PMU VCAMA_PMU VCAM_AF_PMU VCAMD_PMU VCAM_IO_PMU VGP1_PMU VSRAM_PMU
1
1
1
1
1
C0201 C/ 100/ nF/ 0201
D_GND C2031 D_GND
2
C2040 C/ 22/ uF/ 0603 C0603
1
2
2
2
2
2
1
1
C0201
C2030 C/ 100/ nF/ 0201
C/ 1/ uF/ 0201
2
1
1
1
1
1
C0201
C2040 close to AVDD22_LDO1/2/3/4 balls
L3
2
2
2
2
D_GND
GNDA9 B9 C8 C9 D9 B6 C6 D6 C11 D11 D12 A3 B3 A14 B16 AVSS45_VPROC AVSS45_VPROC AVSS45_VPROC AVSS45_VPROC AVSS45_VPROC
Vibrator DriverVIBR J4
GND_VPROC SH2001
Close to MT6328
D_GND
15mil
D_GND
D_GND VIBR_PMU
D_GND
2
D_GND
D_GND VRTC C2008 C/ 22/ uF/ 0603 C0603
2
D_GND
AVSS45_VREF
C2050 C/ 1/ uF/ 0201/ NC C0201
C2047 C/ 1/ uF/ 0201 C0201
C2046 C/ 1/ uF/ 0201 C0201
C2048 C0201 C/ 1/ uF/ 0201/ NC
2
1
2
1
NC/MMD/PMIC
GND_VLTE
XIN XOUT ENBB XOSC_EN
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