GS88136BT-300中文资料(15)

First Write First Read Burst Write Burst Read

Deselect

R W CR

CW X X

W R

R W

R X X X CR R

CW CR

CR W

CW W CW Notes:

1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.

3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)

Rev: 1.05 11/200515/39© 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see . Simplified State Diagram with G

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