GS88136BT-300中文资料(9)

165-Bump BGA Pin Description

Symbol

Type

Description

A 0, A 1I Address field LSBs and Address Counter Preset Inputs

A I Address Inputs DQ A DQ

B DQ

C DQ

D I/O Data Input and Output pins

B A , B B , B

C , B D

I Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low

NC —No Connect

CK I Clock Input Signal; active high

BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low

E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active low

ADV I Burst address counter advance enable; active l0w ADSC, ADSP

I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low

TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect Low V DD I Core power supply V SS I I/O and Core Ground V DDQ

I

Output driver power supply

GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)

Rev: 1.05 11/20059/39© 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see .

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