Fault Sensitivity Analysis and Reliability Enhancement of Analog-to-Digital Converters(8)

Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a

TABLEV

AreaSENSITIVITIESOFFOURCOMPARATORSWITHVARYINGINPUTSFOR4-BITFLASHADC,p=3,q=8,r=4

6005004003002001000

Number of Errors

TABLEVI

1

2

3

4

5

6

7

8

Bit Number

SENSITIVITIESOFTHE4-BITFLASHADCWITHDIFFERENT

COMPARATORS,p=3,q=8,r=4

Fig.22.Variationinnumberoferrorswithtimeforthe -ΣADC,p=3,q=8,r=16

Itisessentialtogaugetheimprovementthateachofthesetech-niquesoffersasthiswouldhelpthedesignertodecideonaneffectivefaulttolerancedesignstrategy.Thefollowingsectionsdescribeseveralredesigntechniques[21]andalsoillustratetheamountofsensitivityimprovementthatcanbegainedbyem-ployingthem.

A.AlternativeRobustImplementations

MostoftheADCbuildingblockslikethesampleandholdampli erandcomparatorshaveseveralpossibleimplementa-tionswhichtrade-offarea,speedandsusceptibilitytonoiseandparametricvariations.Theseimplementationsinherentlyhavedifferentsensitivitiestoα-particletransients.WhendecidingonanimplementationfortheADCinquestion,thesensitivityoffeasibleimplementationsshouldbecomparedandanappro-priateimplementationshouldbechosen.

1)FlashADC:Oursensitivityanalysisofthe4-bitFlashADChasidenti edtheanalogblockprimarilycomprisingofcomparatorsasthecriticalblock.Fourcomparatorswerethenconsideredforsensitivityevaluationtoidentifythemostrobustimplementation.

Tabatabaei’sComparator[18]isarecentimplementationofasinglestagecomparator.Suchsinglestagecomparatorsprovidethedesiredgaininmostcasesbuttheirdelaymaybetoohigh.Toalleviatetheproblemofhighdelay,comparatorswithmulti-plepreampli cationstageshavebeenproposed.Onesuchmul-tistagecomparatorimplementation(Hester’scomparator[20])incorporatespositivefeedbacktoachievethedesiredgain.An-othercomparator(Yee’scomparator[19])usesinvertersbiasedinthehighgainregionaspreampli ers.Thesimplicityofthismultistagecomparatorhasmadeitquitepopularintheresolu-tionrangefrom8to10bits.TableVshowstheresultsofsen-sitivityanalysisofthefouralternativecomparatorimplemen-tations.Theinitialversionofthe4-bit ashADC(discussedFig.23.DigitalDecimationFilterinthe -ΣADC

the -ΣADCrevealedthatthedigitaldecimation lter(de-pictedinFigure23)isthecriticalblock(seeTableIV).There-sultsshownaboveillustratethedifferentkindsofanalysisthatcanbeperformedtoaidthedesignerinarrivingatamorereli-ableimplementation.ThismethodologycanbeusedtoanalyzethefaultsensitivitiesoftheconstituentblocksinanyADCar-chitectureatanearlystageinthedesigncycle,thusreducingconcept-to-silicontime.

IV.RELIABILITYIMPROVEMENTTECHNIQUESAsensitivityanalysisidenti escriticalblocksthatthede-signercanconcentrateontoimprovethereliabilityofthesys-tem.Faulttoleranceofablockcanbeimprovedinoneoftwoways:

1.Evaluatingthesensitivitiesofalternativeimplementationsofablockandselectingthemostrobustimplementation.2.Affectingdesignchangesintheexistingimplementation

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